The present invention relates generally to electronic circuit designs, and more particularly to re-ordering of scan chains in electronic circuit designs.
Scan chains in electronic circuit designs include series-connected scan cells that include one or more flip-flops. Scan chains facilitate testing of a circuit such as a system-on-chip (SoC). Test patterns generated using an external test apparatus are provided to a scan input terminal of a scan chain. An output pattern obtained at a scan output terminal of the scan chain is compared with an expected output pattern to identify possible faults in the circuit design.
Scan chains do not have any digital logic elements between successive scan cells, which renders the scan chain susceptible to hold violations. A hold violation occurs when an intended input of a flip flop in a scan chain is changed before an active clock edge reaches the flip flop, resulting in loss of the intended input. Faster flop access times also contribute to hold violations. To avoid hold violations, one or more buffers are added to the scan chain, which increases the time required for a data signal to propagate through the scan chain. Various on chip variations (OCV) also require addition of buffers to the scan chain, which further increases the time required for the data signal to propagate through the scan chain. Furthermore, the addition of buffers increases the area occupied by the scan chain.
Various scan chain re-ordering techniques are used to optimize the time required for the data signal to propagate in a scan chain and reduce the area occupied by the scan chains. Existing scan chain re-ordering techniques re-order scan chains based on scan chain length and clock tree timing parameters. Clock tree timing parameters include various timing parameters, such as insertion delay associated with the clock tree from which clock signals are provided to the scan chain. The existing scan chain re-ordering techniques are not effective for SoCs that have small circuit boards, where in addition to the clock tree timing parameters, on-chip variations such as inter-die variations, aging margins, negative bias temperature instability, and hot carrier injection also affect the timing parameters. Optimizing timing between successive scan cells of the scan chain after factoring in the OCV requires several manual iterations and is a time consuming task. Thus, there is an increasing need to develop a scan chain re-ordering technique that re-orders the scan chains based on all timing parameters and not just the clock tree timing parameters.
Therefore, it would be advantageous to have a system and method that re-orders scan chains based on the length and various timing parameters, that is not time consuming, and that overcomes the above-mentioned limitations of the existing scan chain re-ordering techniques.